105 search results - page 12 / 21 » Checkpointing alternatives for high performance, power-aware... |
ASAP
2007
IEEE
13 years 9 months ago
2007
IEEE
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
ICPP
2006
IEEE
14 years 1 months ago
2006
IEEE
Multi-lane vector processors achieve excellent computational throughput for programs with high data-level parallelism (DLP). However, application phases without significant DLP ar...
ICPR
2004
IEEE
14 years 8 months ago
2004
IEEE
Real-time image processing tasks not only require high computing power but also high data bandwidth. Though current processors excel in computing power, memory throughput is still...
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
— Dual-radio, dual-processor nodes are an emerging class of Wireless Sensor Network devices that provide both lowenergy operation as well as substantially increased computational...
ISCA
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents Threaded Multi-Path Execution (TME), which exploits existing hardware on a Simultaneous Multithreading (SMT) processor to speculatively execute multiple paths ...