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ICCD
1993
IEEE
90views Hardware» more  ICCD 1993»
14 years 4 days ago
Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequenc...
Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Pee...
PATMOS
2000
Springer
13 years 11 months ago
Early Power Estimation for System-on-Chip Designs
Abstract. Reduction of chip packaging and cooling costs for deep sub-micron SystemOn-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to real...
Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reo...
DATE
2008
IEEE
174views Hardware» more  DATE 2008»
14 years 2 months ago
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment
Due to high demand for hall sensors mostly in the automotive and industrial applications, development and manufacturing of hall sensors in System-on-Chip (SoC) became more importa...
Mustafa Badaroglu, Guy Decabooter, Francois Laulan...
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 1 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
SBCCI
2003
ACM
213views VLSI» more  SBCCI 2003»
14 years 1 months ago
Algorithms and Tools for Network on Chip Based System Design
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
Tang Lei, Shashi Kumar