509 search results - page 38 / 102 » Chip Multi-Processor Generator |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
SP
2010
IEEE
13 years 12 months ago
2010
IEEE
The computer systems security arms race between attackers and defenders has largely taken place in the domain of software systems, but as hardware complexity and design processes ...
DATE
1999
IEEE
14 years 9 days ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
Scan-based silicon debug is a technique that can be used to help find design errors in prototype silicon more quickly. One part of this technique involves the inclusion of breakpo...
CHES
2009
Springer
14 years 8 months ago
2009
Springer
We have devised a frequency injection attack which is able to destroy the source of entropy in ring-oscillator-based true random number generators (TRNGs). A TRNG will lock to freq...