509 search results - page 39 / 102 » Chip Multi-Processor Generator |
ISQED
2002
IEEE
14 years 27 days ago
2002
IEEE
The design methods and the automation of the comparator circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ)...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
We present measured frequency-gain functions and the spike rate outputs of the different sections in a spiking silicon cochlea chip. The chip consists of a matched pair of silicon...
IPPS
2002
IEEE
14 years 27 days ago
2002
IEEE
This paper presents the implementation, on Virtex FPGAs, of a core generator for arbitrary numeric functions in fixed-point format. The cores use the state-of-theart multipartite...
ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
13 years 5 months ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
ESSCIRC
2011
12 years 7 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...