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IEEEPACT
2009
IEEE
13 years 5 months ago
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel...
ARCS
2005
Springer
14 years 1 months ago
Reusable Design of Inter-chip Communication Interfaces for Next Generation of Adaptive Computing Systems
Abstract. The SoC (System-on-Chip) technology is used in small and flexible consumer electronic devices. SoCs include one or more microcontroller, memory, programmable logic, and ...
Vincent Kotzsch, Jörg Schneider, Günther...
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
14 years 28 days ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
14 years 1 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
DAC
2006
ACM
14 years 9 months ago
Scheduling-based test-case generation for verification of multimedia SoCs
Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The v...
Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ron...