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IJPP
2006
82views more  IJPP 2006»
13 years 8 months ago
Supporting Microthread Scheduling and Synchronisation in CMPs
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...
Ian Bell, Nabil Hasasneh, Chris R. Jesshope
MEMOCODE
2003
IEEE
14 years 1 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
DATE
2003
IEEE
145views Hardware» more  DATE 2003»
14 years 1 months ago
Automated Bus Generation for Multiprocessor SoC Design
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...
Kyeong Keol Ryu, Vincent John Mooney
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
14 years 27 days ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 8 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...