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ISPASS
2007
IEEE
14 years 2 months ago
Modeling and Characterizing Power Variability in Multicore Architectures
Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors s...
Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ism...
ESWS
2010
Springer
14 years 22 days ago
Finding Your Way through the Rijksmuseum with an Adaptive Mobile Museum Guide
Abstract. This paper describes a real-time routing system that implements a mobile museum tour guide for providing personalized tours tailored to the user position inside the museu...
Willem Robert van Hage, Natalia Stash, Yiwen Wang,...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 2 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
ICCD
2002
IEEE
115views Hardware» more  ICCD 2002»
14 years 4 months ago
Low-Power, High-Speed CMOS VLSI Design
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
Tadahiro Kuroda
3DIC
2009
IEEE
146views Hardware» more  3DIC 2009»
14 years 2 months ago
A routerless system level interconnection network for 3D integrated systems
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
Kelli Ireland, Donald M. Chiarulli, Steven P. Levi...