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ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
14 years 1 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
DATE
2010
IEEE
142views Hardware» more  DATE 2010»
14 years 1 months ago
Testing TSV-based three-dimensional stacked ICs
To meet customer’s product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone ...
Erik Jan Marinissen
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
14 years 1 days ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
EUROPAR
2006
Springer
13 years 11 months ago
Optimization of Dense Matrix Multiplication on IBM Cyclops-64: Challenges and Experiences
Abstract. This paper presents a study of performance optimization of dense matrix multiplication on IBM Cyclops-64(C64) chip architecture. Although much has been published on how t...
Ziang Hu, Juan del Cuvillo, Weirong Zhu, Guang R. ...
ASPDAC
2001
ACM
105views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Toward better wireload models in the presence of obstacles
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probabil...
Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk S...