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ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 11 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
13 years 11 months ago
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays
We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms used a xed cut line sequence that is determined before min...
Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai...
DAC
2008
ACM
13 years 9 months ago
Protecting bus-based hardware IP by secret sharing
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
TCAD
2010
133views more  TCAD 2010»
13 years 2 months ago
Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization
Protein crystallization is a commonly used technique for protein analysis and subsequent drug design. It predicts the 3-D arrangement of the constituent amino acids, which in turn ...
Tao Xu, Krishnendu Chakrabarty, Vamsee K. Pamula
IPPS
2008
IEEE
14 years 2 months ago
Financial modeling on the cell broadband engine
High performance computing is critical for financial markets where analysts seek to accelerate complex optimizations such as pricing engines to maintain a competitive edge. In th...
Virat Agarwal, Lurng-Kuo Liu, David A. Bader