Sciweavers

509 search results - page 75 / 102
» Chip Multi-Processor Generator
Sort
View

Publication
576views
15 years 7 months ago
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
Brendan Hargreaves, Henrik Hult, Sherief Reda
ICIP
2001
IEEE
14 years 9 months ago
Optical flow estimation using high frame rate sequences
Gradient-based optical flow estimation methods such as LucasKanade method work well for scenes with small displacements but fail when objects move with large displacements. Hierar...
SukHwan Lim, Abbas El Gamal
DAC
2007
ACM
14 years 8 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2003
ACM
14 years 8 months ago
A retargetable micro-architecture simulator
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
Wai Sum Mong, Jianwen Zhu
VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
14 years 8 months ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal