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DAC
2010
ACM
13 years 11 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
CASES
2004
ACM
13 years 11 months ago
Automatic data partitioning for the agere payload plus network processor
With the ever-increasing pervasiveness of the Internet and its stringent performance requirements, network system designers have begun utilizing specialized chips to increase the ...
Steve Carr, Philip H. Sweany
TAPSOFT
1995
Springer
13 years 11 months ago
Anatomy of the Pentium Bug
The Pentium computer chip’s division algorithm relies on a table from which five entries were inadvertently omitted, with the result that 1738 single precision dividenddivisor ...
Vaughan R. Pratt
ATAL
2008
Springer
13 years 9 months ago
Decentralised coordination of low-power embedded devices using the max-sum algorithm
This paper considers the problem of performing decentralised coordination of low-power embedded devices (as is required within many environmental sensing and surveillance applicat...
Alessandro Farinelli, Alex Rogers, Adrian Petcu, N...
CASES
2008
ACM
13 years 9 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...