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MICRO
2008
IEEE
119views Hardware» more  MICRO 2008»
14 years 2 months ago
The StageNet fabric for constructing resilient multicore systems
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
ICPPW
2007
IEEE
14 years 2 months ago
Power Management of Multicore Multiple Voltage Embedded Systems by Task Scheduling
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
Gang Qu
ISVLSI
2007
IEEE
150views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Minimum-Congestion Placement for Y-interconnects: Some studies and observations
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Pa...
CODES
2006
IEEE
14 years 1 months ago
Multi-processor system design with ESPAM
For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by emb...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
14 years 1 months ago
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs
This paper describes a fast-lock mixed-mode delaylocked loop (MMDLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time...
Kuo-Hsing Cheng, Yu-lung Lo