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    RECONFIG
    2008
    IEEE
    268views VLSI» more  RECONFIG 2008»
    Parametric, Secure and Compact Implementation of RSA on FPGA
    14 years 1 months ago
    Parametric, Secure and Compact Implementation of RSA on FPGA
    Download  research.sabanciuniv.edu
    1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
    Ersin Oksuzoglu, Erkay Savas
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    DATE
    2004
    IEEE
    210views Hardware» more  DATE 2004»
    Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
    13 years 11 months ago
    Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
    Download  mesl.ucsd.edu
    Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...
    Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru N...
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    FPGA
    2011
    ACM
    393views FPGA» more  FPGA 2011»
    Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
    12 years 11 months ago
    Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
    Download  www.stuffedcow.net
    As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This pa...
    Henry Wong, Vaughn Betz, Jonathan Rose
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    FCCM
    2005
    IEEE
    139views VLSI» more  FCCM 2005»
    A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
    14 years 1 months ago
    A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
    Download  www.cs.ucr.edu
    Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
    Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
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    DAC
    1998
    ACM
    131views Computer Architecture» more  DAC 1998»
    Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
    13 years 11 months ago
    Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
    Download  www.cs.york.ac.uk
    We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
    Ganesh Lakshminarayana, Niraj K. Jha
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