96 search results - page 15 / 20 » Circuit modeling for practical many-core architecture design... |
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified Si...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
SIGGRAPH
1995
ACM
13 years 11 months ago
1995
ACM
Physically-based modeling has been used in the past to support a variety of interactive modeling tasks including free-form surface design, mechanism design, constrained drawing, a...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
ISPD
2007
ACM
13 years 9 months ago
2007
ACM
In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture plac...