96 search results - page 6 / 20 » Circuit modeling for practical many-core architecture design... |
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
DAC
2003
ACM
14 years 28 days ago
2003
ACM
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
SIGCSE
2008
ACM
13 years 7 months ago
2008
ACM
While the demand for college graduates with computing skills continues to rise, such skills no longer equate to mere programming skills. Modern day computing jobs demand design, c...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...