253 search results - page 14 / 51 » Circuit partitions and |
TCAD
1998
13 years 7 months ago
1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
In this paper we present a set cover based approach (SCP) to multi-way partitioning for minimum delay for Look-Up Table based FPGAs. SCP minimizes the number of chip-crossings on ...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...