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VLSID
2003
IEEE
144views VLSI» more  VLSID 2003»
16 years 6 months ago
The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance
In this paper, we provide an analytical framework to study the inter-cell and intra-cell bit-line coupling when it is superimposed with the ground bounce effect and show how those...
Li Ding 0002, Pinaki Mazumder
VLSID
2003
IEEE
115views VLSI» more  VLSID 2003»
16 years 6 months ago
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
W. Kuang, J. S. Yuan
VLSID
2003
IEEE
148views VLSI» more  VLSID 2003»
16 years 6 months ago
Extending Platform-Based Design to Network on Chip Systems
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
Juha-Pekka Soininen, Axel Jantsch, Martti Forsell,...
VLSID
2002
IEEE
129views VLSI» more  VLSID 2002»
16 years 6 months ago
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylves...
VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
16 years 6 months ago
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications
Embedded DRAM (eDRAM) power-energy estimation is presented for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improve...
Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo