In this paper, we provide an analytical framework to study the inter-cell and intra-cell bit-line coupling when it is superimposed with the ground bounce effect and show how those...
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
Juha-Pekka Soininen, Axel Jantsch, Martti Forsell,...
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylves...
Embedded DRAM (eDRAM) power-energy estimation is presented for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improve...