Sciweavers

    3395 search results - page 558 / 679
    » Circuit-aware architectural simulation
    Sort
    View
    DAC
    2008
    ACM
    136views Computer Architecture» more  DAC 2008»
    Feedback-controlled reliability-aware power management for real-time embedded systems
    14 years 9 months ago
    Feedback-controlled reliability-aware power management for real-time embedded systems
    Download  research.cs.tamu.edu
    In recent literature it has been reported that Dynamic Power Management (DPM) may lead to decreased reliability in real-time embedded systems. The ever-shrinking device sizes cont...
    Ranjani Sridharan, Nikhil Gupta, Rabi N. Mahapatra
    claim paper
    Read More »
    DAC
    2008
    ACM
    146views Computer Architecture» more  DAC 2008»
    Miss reduction in embedded processors through dynamic, power-friendly cache design
    14 years 9 months ago
    Miss reduction in embedded processors through dynamic, power-friendly cache design
    Download  cseart.ucsd.edu
    Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
    Garo Bournoutian, Alex Orailoglu
    claim paper
    Read More »
    DAC
    2008
    ACM
    149views Computer Architecture» more  DAC 2008»
    Automatic synthesis of clock gating logic with controlled netlist perturbation
    14 years 9 months ago
    Automatic synthesis of clock gating logic with controlled netlist perturbation
    Download  www.eecs.berkeley.edu
    Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
    Aaron P. Hurst
    claim paper
    Read More »
    DAC
    2008
    ACM
    143views Computer Architecture» more  DAC 2008»
    Driver waveform computation for timing analysis with multiple voltage threshold driver models
    14 years 9 months ago
    Driver waveform computation for timing analysis with multiple voltage threshold driver models
    Download  www.ece.northwestern.edu
    This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
    Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
    claim paper
    Read More »
    DAC
    2008
    ACM
    148views Computer Architecture» more  DAC 2008»
    Construction of concrete verification models from C++
    14 years 9 months ago
    Construction of concrete verification models from C++
    Download  www.cse.iitd.ernet.in
    C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
    Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, ...
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.