3395 search results - page 77 / 679 » Circuit-aware architectural simulation |
145
click to vote
LCTRTS
2004
Springer
15 years 9 months ago
2004
Springer
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
127
click to vote
E4MAS
2005
Springer
15 years 10 months ago
2005
Springer
In this paper we discuss the model of an environment, acting as a first-class entity for MAS Simulation. To illustrate, we use the DIVAs framework’s design and implementation de...
133
click to vote
DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
150
click to vote
IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
1 Multi-paradigm, multi-threaded and multi-core computing devices available today provide several orders of magnitude performance improvement over mainstream microprocessors. These...
140
click to vote
ISQED
2006
IEEE
15 years 10 months ago
2006
IEEE
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...