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ISLPED
1995
ACM
116views Hardware» more  ISLPED 1995»
15 years 8 months ago
Activity-sensitive architectural power analysis for the control path
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing ...
Paul E. Landman, Jan M. Rabaey
CORR
2007
Springer
120views Education» more  CORR 2007»
15 years 4 months ago
Remote laboratories: new technology and standard based architecture
E-Laboratories are important components of elearning environments, especially in scientific and technical disciplines. First widespread E-Labs consisted in proposing simulations o...
Hcene Benmohamed, Arnaud Lelevé, Patrick Pr...
IJDSN
2007
111views more  IJDSN 2007»
15 years 4 months ago
Architecture of Wireless Sensor Networks with Mobile Sinks: Multiple Access Case
We propose to develop wireless Sensor Networks with Mobile Sinks (MSSN), under high sensor node density, where multiple sensor nodes need to share one single communication channel...
Liang Song, Dimitrios Hatzinakos
TVLSI
2002
121views more  TVLSI 2002»
15 years 4 months ago
On-chip decoupling capacitor optimization using architectural level prediction
Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular techniq...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills
JUCS
2000
120views more  JUCS 2000»
15 years 4 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi