Sciweavers

197 search results - page 17 / 40
» Circuits, Pebbling and Expressibility
Sort
View
ICCD
2004
IEEE
115views Hardware» more  ICCD 2004»
14 years 4 months ago
Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs
Formal and dynamic (simulation, emulation, etc.) verification techniques are both needed to deal with the overall challenge of verification. Ideally, the same specification/tes...
Kelvin Ng, Alan J. Hu, Jin Yang
ISCAS
2006
IEEE
86views Hardware» more  ISCAS 2006»
14 years 1 months ago
Fast timing analysis of plane circuits via two-layer CNN-based modeling
Abstract— A fast timing analysis of plane circuits via two-layer CNNbased modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boar...
Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifum...
CRYPTO
2005
Springer
127views Cryptology» more  CRYPTO 2005»
14 years 1 months ago
One-Way Secret-Key Agreement and Applications to Circuit Polarization and Immunization of Public-Key Encryption
Secret-key agreement between two parties Alice and Bob, connected by an insecure channel, can be realized in an informationtheoretic sense if the parties share many independent pai...
Thomas Holenstein, Renato Renner
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Novel dual-Vth independent-gate FinFET circuits
This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enabl...
Masoud Rostami, Kartik Mohanram
DAC
1999
ACM
14 years 8 months ago
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman