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» Circuits, Pebbling and Expressibility
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DAC
2000
ACM
14 years 8 months ago
The use of carry-save representation in joint module selection and retiming
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
14 years 4 months ago
Block-based Static Timing Analysis with Uncertainty
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
Anirudh Devgan, Chandramouli V. Kashyap
ICTAI
2009
IEEE
14 years 2 months ago
Emergence of Memory-like Behavior in Reactive Agents Using External Markers
Early primitive animals with simple feed-forward neuronal circuits were limited to reactive behavior. Through evolution, they were gradually equipped with memory and became able t...
Ji Ryang Chung, Yoonsuck Choe
ISCAS
2008
IEEE
104views Hardware» more  ISCAS 2008»
14 years 1 months ago
An offset compensation technique for bandgap voltage reference in CMOS technology
— A precision integrated bandgap voltage reference in 0.35μm CMOS technology is here presented. The circuit uses natural npn bipolar transistors as reference diodes. A particula...
Stefano Ruzza, Enrico Dallago, Giuseppe Venchi, Se...
GLVLSI
2003
IEEE
175views VLSI» more  GLVLSI 2003»
14 years 24 days ago
A custom FPGA for the simulation of gene regulatory networks
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
Ilias Tagkopoulos, Charles A. Zukowski, German Cav...