In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...
N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheun...