205 search results - page 25 / 41 » Clock gating architectures for FPGA power reduction |
FPGA
2009
ACM
14 years 5 months ago
2009
ACM
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
DAC
2003
ACM
14 years 11 months ago
2003
ACM
The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limit...
DATE
2007
IEEE
14 years 5 months ago
2007
IEEE
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
FPGA
2008
ACM
14 years 10 days ago
2008
ACM
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
DAC
1997
ACM
14 years 2 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...