205 search results - page 26 / 41 » Clock gating architectures for FPGA power reduction |
ISLPED
1995
ACM
14 years 2 months ago
1995
ACM
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
ASPDAC
2005
ACM
14 years 23 days ago
2005
ACM
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...
ISCA
2002
IEEE
14 years 3 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
VLSID
2004
IEEE
14 years 11 months ago
2004
IEEE
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...
DATE
2000
IEEE
14 years 3 months ago
2000
IEEE
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...