205 search results - page 29 / 41 » Clock gating architectures for FPGA power reduction |
VLSID
2002
IEEE
14 years 11 months ago
2002
IEEE
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
FPGA
2000
ACM
14 years 2 months ago
2000
ACM
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
ICCAD
2002
IEEE
14 years 7 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
CODES
2008
IEEE
14 years 5 months ago
2008
IEEE
Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ...
ICES
2005
Springer
14 years 4 months ago
2005
Springer
Abstract. There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip e...