96 search results - page 6 / 20 » Clock-Aware Placement for FPGAs |
FPL
2006
Springer
13 years 11 months ago
2006
Springer
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
FPGA
1998
ACM
13 years 11 months ago
1998
ACM
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA...
FPL
2004
Springer
14 years 22 days ago
2004
Springer
Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement s...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...