96 search results - page 7 / 20 » Clock-Aware Placement for FPGAs |
ERSA
2004
13 years 8 months ago
2004
This paper introduces VTsim, a device simulator for Xilinx Virtex-II FPGAs. VTsim is currently a globally synchronous event-driven device simulator modeled at the CLB level. Throu...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Partially reconfigurable Field-Programmable Gate Arrays (FPGAs) allow parts of the chip to be configured at run-time where each part could hold an independent task. Online place...
ERSA
2006
13 years 8 months ago
2006
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
FPGA
2003
ACM
14 years 17 days ago
2003
ACM
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer line...