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ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
15 years 12 months ago
Glitch-aware output switching activity from word-level statistics
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
Jonathan A. Clarke, George A. Constantinides, Pete...
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
16 years 2 months ago
Robust analog/RF circuit design with projection-based posynomial modeling
In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthe...
Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence ...
PADS
2006
ACM
15 years 11 months ago
A Framework for Robust HLA-based Distributed Simulations
The High Level Architecture (HLA) is a standard for the interoperability and reuse of simulation components, referred to as federates. Large scale HLA-compliant simulations are bu...
Dan Chen, Stephen John Turner, Wentong Cai
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
16 years 2 months ago
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
131
Voted
ACSC
2005
IEEE
15 years 11 months ago
Simulating Network Robustness for Critical Infrastructure Networks
We examine the robustness of critical infrastructure networks in the face of terrorist attack, using a simulation experiment that incorporates link capacity; and an extension of d...
Anthony H. Dekker