47 search results - page 5 / 10 » Co-design of interleaved memory systems |
ISCA
2010
IEEE
14 years 17 days ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ISCA
2002
IEEE
13 years 7 months ago
2002
IEEE
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...
CONCURRENCY
2006
13 years 7 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
TCOM
2010
13 years 2 months ago
2010
It has been widely acknowledged that the aggregate interference at the receiver for various practical communication channels can often deviate markedly from the classical additive ...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
We consider self-testing of complete wireless nodes in the field through a low-energy software-based selftest (SBST) method. Energy consumption is optimized both for individual co...