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» Co-synthesis with custom ASICs
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DSD
2008
IEEE
110views Hardware» more  DSD 2008»
13 years 11 months ago
VLSI Implementation of a Cryptography-Oriented Reconfigurable Array
The long-word and very long-word addition required in cryptography applications generally requires custom hardware support provided by ASICs or application-specific instructions i...
Scott Miller, Ambrose Chu, Mihai Sima, Michael McG...
ISVLSI
2006
IEEE
126views VLSI» more  ISVLSI 2006»
14 years 3 months ago
QUKU: A Two-Level Reconfigurable Architecture
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker
ISCA
2003
IEEE
112views Hardware» more  ISCA 2003»
14 years 3 months ago
A Pipelined Memory Architecture for High Throughput Network Processors
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
Timothy Sherwood, George Varghese, Brad Calder
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
14 years 2 months ago
Detailed routing architectures for embedded programmable logic IP cores
As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be real...
Peter Hallschmid, Steven J. E. Wilton
ISCA
2007
IEEE
106views Hardware» more  ISCA 2007»
14 years 4 months ago
Architectural implications of brick and mortar silicon manufacturing
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, ...