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» Co-synthesis with custom ASICs
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GLVLSI
2002
IEEE
127views VLSI» more  GLVLSI 2002»
14 years 2 months ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
John A. Nestor
IPPS
2000
IEEE
14 years 2 months ago
A Distributed Computing Demonstration System Using FSOI Inter-processor Communication
Presented here is a computational system which uses free−space optical interconnect (FSOI) communication between processing elements to perform distributed calculations. Technolo...
Jeremy Ekman, Christoph Berger, Fouad E. Kiamilev,...
VLSID
2002
IEEE
92views VLSI» more  VLSID 2002»
14 years 10 months ago
Low Power Solution for Wireless Applications
Low standby power dissipation is the primary need for most of the wireless applications for prolonged battery life. Traditionally ASIC solutions currently address either high densi...
Sornavalli Ramanathan, Rituparna Mandal
CASES
2004
ACM
14 years 3 months ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker
HPCA
2009
IEEE
14 years 10 months ago
Bridging the computation gap between programmable processors and hardwired accelerators
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Sco...