62 search results - page 9 / 13 » Co-synthesis with custom ASICs |
TODAES
2008
13 years 9 months ago
2008
The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integ...
SIGCOMM
2009
ACM
14 years 4 months ago
2009
ACM
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
FPGA
2010
ACM
14 years 6 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
DAC
2007
ACM
14 years 10 months ago
2007
ACM
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...