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SCAM
2005
IEEE
14 years 1 months ago
Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions
Most software for embedded systems, including digital signal processing systems, is coded in assembly language. For both understanding the software and for reverse compiling it to...
Nerina Bermudo, Andreas Krall, R. Nigel Horspool
MICRO
1992
IEEE
128views Hardware» more  MICRO 1992»
13 years 11 months ago
MISC: a Multiple Instruction Stream Computer
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz...
SC
2000
ACM
13 years 11 months ago
High Performance Reactive Fluid Flow Simulations Using Adaptive Mesh Refinement on Thousands of Processors
We present simulations and performance results of nuclear burning fronts in supernovae on the largest domain and at the finest spatial resolution studied to date. These simulation...
A. C. Calder, Bruce C. Curtis, L. J. Dursi, Bruce ...
DATE
2002
IEEE
137views Hardware» more  DATE 2002»
14 years 11 days ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten
EMSOFT
2004
Springer
14 years 24 days ago
An approach for integrating basic retiming and software pipelining
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
Noureddine Chabini, Wayne Wolf