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HICSS
1995
IEEE
128views Biometrics» more  HICSS 1995»
13 years 11 months ago
Instruction Level Parallelism
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
RSP
2006
IEEE
120views Control Systems» more  RSP 2006»
14 years 1 months ago
A Case Study of Design Space Exploration for Embedded Multimedia Applications on SoCs
Embedded real-time multimedia applications usually imply data parallel processing. SIMD processors embedded in SOCs are cost-effective to exploit the underlying parallelism. Howev...
Isabelle Hurbain, Corinne Ancourt, François...
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
13 years 11 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
14 years 7 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
VISUALIZATION
2002
IEEE
14 years 9 days ago
Interactive Rendering of Large Volume Data Sets
We present a new algorithm for rendering very large volume data sets at interactive framerates on standard PC hardware. The algorithm accepts scalar data sampled on a regular grid...
Stefan Guthe, Michael Wand, Julius Gonser, Wolfgan...