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» Code Generation for Embedded Processors
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ICCD
2007
IEEE
152views Hardware» more  ICCD 2007»
14 years 18 days ago
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors
As application-specific instruction set processors (ASIPs) are being increasingly used in mobile embedded systems, the ubiquitous networking connections have exposed these systems...
Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi
RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
14 years 2 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 2 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
FCCM
2009
IEEE
190views VLSI» more  FCCM 2009»
14 years 3 months ago
Optical Flow on the Ambric Massively Parallel Processor Array (MPPA)
The Ambric Massively Parallel Processor Array (MPPA) is a device that contains 336 32-bit RISC processors and is appropriate for embedded systems due to its relatively small physi...
Brad L. Hutchings, Brent E. Nelson, Stephen West, ...
PAAPP
2006
44views more  PAAPP 2006»
13 years 8 months ago
Revisiting communication code generation algorithms for message-passing systems
In this paper, we investigate algorithms for generating communication code to run on distributedmemory systems. We modify algorithms from previously published work and prove that ...
Clayton S. Ferner