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CSSE
2008
IEEE
14 years 3 months ago
Generation of Executable Representation for Processor Simulation with Dynamic Translation
Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive...
Jiajia Song, HongWei Hao, Claude Helmstetter, Vani...
DDECS
2008
IEEE
227views Hardware» more  DDECS 2008»
13 years 10 months ago
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator
The paper introduces a cryptographic System on a Chip (SoC) implementation based on recent Actel nonvolatile FPGA Fusion chip with embedded ARM7 soft-core processor. The SoC is bui...
Milos Drutarovsky, Michal Varchola
CODES
2007
IEEE
14 years 3 months ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
14 years 1 months ago
Control generation for embedded systems based on composition of modal processes
In traditional distributed embedded system designs, control information is often replicated across several processes and kept coherent by application-specific mechanisms. Conseque...
Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Bo...
SAMOS
2004
Springer
14 years 2 months ago
A Low-Power Multithreaded Processor for Baseband Communication Systems
Embedded digital signal processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low inter...
Michael J. Schulte, C. John Glossner, Suman Mamidi...