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» Code Generation for Embedded Processors
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PLDI
2004
ACM
14 years 2 months ago
Fast searches for effective optimization phase sequences
It has long been known that a fixed ordering of optimization phases will not produce the best code for every application. One approach for addressing this phase ordering problem ...
Prasad Kulkarni, Stephen Hines, Jason Hiser, David...
ISCA
2003
IEEE
107views Hardware» more  ISCA 2003»
14 years 2 months ago
Positional Adaptation of Processors: Application to Energy Reduction
Although adaptive processors can exploit application variability to improve performance or save energy, effectively managing their adaptivity is challenging. To address this probl...
Michael C. Huang, Jose Renau, Josep Torrellas
VLSISP
2008
123views more  VLSISP 2008»
13 years 8 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
ISCAS
1999
IEEE
113views Hardware» more  ISCAS 1999»
14 years 1 months ago
Energy efficient software through dynamic voltage scheduling
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
Gangadhar Konduri, James Goodman, Anantha Chandrak...
ISLPED
1999
ACM
100views Hardware» more  ISLPED 1999»
14 years 1 months ago
Selective instruction compression for memory energy reduction in embedded systems
We propose a technique for reducing the energy required by rmware code to execute on embedded systems. The method is based on the idea of compressing the most commonly executed in...
Luca Benini, Alberto Macii, Enrico Macii, Massimo ...