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» Code Transformations to Improve Memory Parallelism
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CODES
2005
IEEE
14 years 2 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
ISCA
2012
IEEE
281views Hardware» more  ISCA 2012»
11 years 11 months ago
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a l...
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev B...
ECOOPW
1999
Springer
14 years 28 days ago
Tool Support for Refactoring Duplicated OO Code
Code duplication is an important problem in application maintenance. Tools exist that support code duplication detection. However, few of them propose a solution for the problem, ...
Matthias Rieger, Stéphane Ducasse, Georges ...
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
14 years 1 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
14 years 2 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...