135 search results - page 10 / 27 » Code and Data Transformations for Improving Shared Cache Per... |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
IEEEPACT
2009
IEEE
13 years 5 months ago
2009
IEEE
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
ISCAPDCS
2003
13 years 8 months ago
2003
Data intensive service functions such as memory allocation/de-allocation, data prefetching, and data relocation can pollute processor cache in conventional systems since the same ...
ISCAPDCS
2003
13 years 8 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...