135 search results - page 10 / 27 » Code and Data Transformations for Improving Shared Cache Per... |
132
Voted
DAC
2008
ACM
16 years 4 months ago
2008
ACM
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
159
Voted
IEEEPACT
2009
IEEE
15 years 1 months ago
2009
IEEE
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
138
Voted
ISCAPDCS
2003
15 years 5 months ago
2003
Data intensive service functions such as memory allocation/de-allocation, data prefetching, and data relocation can pollute processor cache in conventional systems since the same ...
153
Voted
ISCAPDCS
2003
15 years 5 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
134
Voted
ASPLOS
2008
ACM
15 years 5 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...