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134
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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 8 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
124
Voted
TON
2002
175views more  TON 2002»
15 years 3 months ago
Compressed bloom filters
A Bloom filter is a simple space-efficient randomized data structure for representing a set in order to support membership queries. Although Bloom filters allow false positives, f...
Michael Mitzenmacher
135
Voted
DSL
1997
15 years 5 months ago
Experience with a Language for Writing Coherence Protocols
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...
Satish Chandra, James R. Larus, Michael Dahlin, Br...
180
Voted
WIA
2004
Springer
15 years 9 months ago
A BDD-Like Implementation of an Automata Package
In this paper we propose a new data structure, called shared automata, for representing deterministic finite automata (DFA). Shared automata admit a strong canonical form for DFA ...
Jean-Michel Couvreur
155
Voted
CODES
2004
IEEE
15 years 7 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis