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» Code compression for low power embedded system design
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CODES
2006
IEEE
14 years 2 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
CASES
2007
ACM
14 years 16 days ago
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control
Micro-Electro-Mechanical Systems (MEMS) combine lithographically formed mechanical structures with electrical elements to create physical systems that operate on the scale of micr...
Greg Hoover, Forrest Brewer, Timothy Sherwood
CHI
2005
ACM
14 years 9 months ago
A logic block enabling logic configuration by non-experts in sensor networks
Recent years have seen the evolution of networks of tiny low power computing blocks, known as sensor networks. In one class of sensor networks, a non-expert user, who has little o...
Susan Cotterell, Frank Vahid
VTS
2005
IEEE
95views Hardware» more  VTS 2005»
14 years 2 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...
NJC
2000
169views more  NJC 2000»
13 years 8 months ago
A Type System for Bounded Space and Functional In-Place Update
We show how linear typing can be used to obtain functional programs which modify heap-allocated data structures in place. We present this both as a "design pattern" for ...
Martin Hofmann