31 search results - page 5 / 7 » Code generation schema for modulo scheduled loops |
ICPADS
2006
IEEE
14 years 3 months ago
2006
IEEE
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
ISSS
1999
IEEE
14 years 2 months ago
1999
IEEE
Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity o...
CONCURRENCY
2006
13 years 9 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
CC
2006
Springer
14 years 1 months ago
2006
Springer
The polyhedral model is known to be a powerful framework to reason about high level loop transformations. Recent developments in optimizing compilers broke some generally accepted ...
PLDI
1995
ACM
14 years 1 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...