133 search results - page 15 / 27 » Code restructuring for improving cache performance of MPSoCs |
100
Voted
DAC
2004
ACM
16 years 3 months ago
2004
ACM
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
134
Voted
ICS
1999
Tsinghua U.
15 years 6 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
132
Voted
DSN
2009
IEEE
15 years 6 months ago
2009
IEEE
In large storage systems, it is crucial to protect data from loss due to failures. Erasure codes lay the foundation of this protection, enabling systems to reconstruct lost data w...
140
Voted
ISCA
1996
IEEE
15 years 6 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
120
Voted
ASPLOS
2008
ACM
15 years 4 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...