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TVLSI
2010
13 years 2 months ago
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this ga...
Peter A. Jamieson, Jonathan Rose
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
14 years 27 days ago
Register binding and port assignment for multiplexer optimization
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
Deming Chen, Jason Cong
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
13 years 11 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
CSCW
2007
ACM
13 years 7 months ago
Supporting Community Emergency Management Planning through a Geocollaboration Software Architecture
Emergency management is more than just events occurring within an emergency situation. It encompasses a variety of persistent activities such as planning, training, assessment, and...
Wendy A. Schafer, Craig H. Ganoe, John M. Carroll
DATE
2008
IEEE
76views Hardware» more  DATE 2008»
14 years 1 months ago
Front End Device for Content Networking
The bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. T...
Jeremy Buboltz, Taskin Koçak