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SIAMSC
2010
140views more  SIAMSC 2010»
13 years 5 months ago
Parallel High-Order Integrators
In this work we discuss a class of defect correction methods which is easily adapted to create parallel time integrators for multi-core architectures and is ideally suited for deve...
Andrew J. Christlieb, Colin B. Macdonald, Benjamin...
HPCA
2008
IEEE
14 years 7 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
ACIVS
2005
Springer
14 years 1 months ago
Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures
Abstract. Image processing is widely used in many applications, including medical imaging, industrial manufacturing and security systems. In these applications, the size of the ima...
Hamed Fatemi, Henk Corporaal, Twan Basten, Richard...
IPPS
2009
IEEE
14 years 2 months ago
Power-aware dynamic task scheduling for heterogeneous accelerated clusters
Recent accelerators such as GPUs achieve better cost-performance and watt-performance ratio, while the range of their application is more limited than general CPUs. Thus heterogen...
Tomoaki Hamano, Toshio Endo, Satoshi Matsuoka
ICPPW
2009
IEEE
13 years 5 months ago
Improvement of Messages Delivery Time on Vehicular Delay-Tolerant Networks
Vehicular Delay-Tolerant Networks (VDTNs) are an application of the Delay-Tolerant Network (DTN) concept, where the movement of vehicles and their message relaying service is used ...
Vasco Nuno da Gama de Jesus Soares, Joel Jos&eacut...