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DATE
2004
IEEE
184views Hardware» more  DATE 2004»
14 years 8 days ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
14 years 7 days ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
ESOP
2008
Springer
13 years 10 months ago
Verification of Higher-Order Computation: A Game-Semantic Approach
Abstract. We survey recent developments in an approach to the verification of higher-order computation based on game semantics. Higherorder recursion schemes are in essence (progra...
C.-H. Luke Ong
DAC
2006
ACM
14 years 9 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
CORR
2010
Springer
208views Education» more  CORR 2010»
13 years 8 months ago
Bounded Model Checking of Multi-threaded Software using SMT solvers
The transition from single-core to multi-core processors has made multi-threaded software an important subject in computer aided verification. Here, we describe and evaluate an ex...
Lucas Cordeiro, Bernd Fischer 0002