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SBCCI
2009
ACM
188views VLSI» more  SBCCI 2009»
14 years 1 months ago
Low-power inter-core communication through cache partitioning in embedded multiprocessors
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
Chenjie Yu, Xiangrong Zhou, Peter Petrov
ISCAS
2006
IEEE
157views Hardware» more  ISCAS 2006»
14 years 1 months ago
DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
Daewook Kim, Manho Kim, Gerald E. Sobelman
SDL
2007
192views Hardware» more  SDL 2007»
13 years 8 months ago
OpenComRTOS: An Ultra-Small Network Centric Embedded RTOS Designed Using Formal Modeling
Abstract. OpenComRTOS is one of the few Real-Time Operating Systems (RTOS) for embedded systems that was developed using formal modeling techniques. The goal was to obtain a proven...
Eric Verhulst, Gjalt G. de Jong
ICIP
1999
IEEE
14 years 8 months ago
Architecture of Embedded Video Processing in a Multimedia Chip-Set
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
Egbert G. T. Jaspers, Peter H. N. de With
CODES
2002
IEEE
14 years 10 hour ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh