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DATE
2000
IEEE
110views Hardware» more  DATE 2000»
14 years 12 days ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann
INFOCOM
1999
IEEE
14 years 8 days ago
A Model for Window Based Flow Control in Packet-Switched Networks
Recently, networks have increased rapidly both in scale and speed. Problems related to the control and management are of increasing interest. The average throughput and end-to-end ...
Xiaowei Yang
EDCC
1999
Springer
14 years 8 days ago
A Fault Tolerant Clock Synchronization Algorithm for Systems with Low-Precision Oscillators
In this paper we present a new fault tolerant clock synchronization algorithm called the Fault Tolerant Daisy Chain algorithm. It is intended for internal clock synchronization of...
Henrik Lönn
CONEXT
2008
ACM
13 years 9 months ago
ALPHA: an adaptive and lightweight protocol for hop-by-hop authentication
Wireless multi-hop networks are particularly susceptible to attacks based on flooding and the interception, tampering with, and forging of packets. Thus, reliable communication in...
Tobias Heer, Stefan Götz, Oscar García...
WSC
2004
13 years 9 months ago
An Architecture for Distributed Simulation Games
In this paper we present an architecture for internet-mediated simulation games. The challenge was to use today's state of the art technologies to provide a simulated environ...
Stijn-Pieter A. van Houten, Peter H. M. Jacobs