138 search results - page 5 / 28 » Compaction-based test generation using state and fault infor... |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspecific spectral information in th...
TC
1998
13 years 7 months ago
1998
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
ICSEA
2006
IEEE
14 years 1 months ago
2006
IEEE
— This paper describes an innovative approach to network testing based on automatically generating and analyzing state machine models of network behavior. The models are generate...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ICDCS
1993
IEEE
13 years 11 months ago
1993
IEEE
In this paper, we propose a diagnostic algorithm for the case where distributed system specifications (implementations) are given in the form of communicating finite state machine...